1. Field
This disclosure relates to manufacturing of power devices and, specifically, for manufacturing of large diameter wafers used for power devices.
2. Related Art
Silicon carbide, SiC, is a crystalline semiconductor material, recognized by those familiar with materials science, electronics and physics as being advantageous for wide band gap properties and also for extreme hardness, high thermal conductivity and chemical inert properties. These properties make SiC a very attractive semiconductor for fabrication of power semiconductor devices, enabling power density and performance enhancement over devices made from more common materials like silicon.
The most common forms of SiC consist of cubic or hexagonal arrangements of atoms. The stacking of Si and C layers can take on many forms, known as polytypes. The type of silicon carbide crystal is denoted by a number denoting the number of repeat units in the stacking sequence followed by a letter representing the crystalline format. For example the 3C—SiC polytype refers to a repeat unit of 3 and a cubic (C) lattice, while a 4H—SiC polytype refers to repeat unit of 4 and a hexagonal (H) lattice.
The different silicon carbide polytypes have some variations in materials properties, most notably electrical properties. The 4H—SiC polytype has the relatively larger bandgap while the 3C—SiC has a smaller bandgap, with the bandgaps for most other polytypes falling in between. For high performance power device applications when the bandgap is larger, the material is more capable, in theory, to offer relatively better high power and thermal conductivity performance.
SiC crystals do not occur in nature and as such must be synthesized. Growth of SiC crystals can be executed by sublimation, also referred to as physical vapor transport, or chemical vapor deposition.
Growth of SiC by sublimation is very challenging. Temperatures in excess of 2000 C are required to generate as vapor stream of Si and C species by sublimation, which places great limitations on the reaction cell components and the furnace design. Originally SiC abrasive materials formed by processes like the Acheson method were used as the source of the Si and C atoms for the crystal, and as the technology matured groups developed means to synthesize SiC source powder specifically for SiC crystal growth. The growth is usually performed in a graphite container within a vacuum chamber. The graphite container is heated by either resistive methods or induction methods. The container is insulated in a careful manner so as to create controlled temperature gradients within the volume. A seed crystal is used and usually shaped like a plate or disc. The seed crystal is typically oriented with its growth surface facing the source material. The location of the seed crystal in the container is designed such that when the container is heated the seed is at a relatively lower temperature position, while the Si-C source materials are at the higher temperature position. When the container is heated to a temperature sufficient to sublime the source material, the vapors will travel towards the low temperature region and condense on the seed crystal. While this appears simple in concept, in practice the growth of SiC is very complicated and recognized by those who practice as very difficult to perform.
Historically, initial progress in SiC sublimation-based crystal growth is described first by Lely (U.S. Pat. No. 2,854,364—1958) whose method of unseeded crystal growth resulted in small hexagonal SiC platelets. In the 1970s and 1980s the art to produce the first crystals of size attractive for producing devices was done in Russia by Tairov and Tsvetkov (Journal of Crystal Growth, 52 (1981) p. 146-50 and Progress in Controlling the Growth of Polytypic Crystals in Crystal Growth and Characterization of Polytype Structures, P. Krishna, ed., Pergammon Press, London, p. 111 (1983)). Their approach used a Lely crystal as a seed, and conducted growth by sublimation and transport as described above. These results showed methods for polytype control by choice of seeds, pressure control and temperature gradients. Later, Davis (U.S. Pat. No. 4,866,005—1989) revealed improvements by judicious selection of source materials and gradient controls. Refinements on the methods of Tairov, Tsvetkov and Davis continue to be revealed to this day.
FIG. 1 illustrates a generic arrangement for growth of SiC crystals by physical vapor transport, indicative of the prior art. PVT reaction cell 40 having lid 55 is illustrated which is configured for SiC crystal growth. The reaction cell 40 is typically formed from a graphite vessel. Granulized SiC or silicon and carbon material 42 is placed in the bottom of the cell. Positioned in the upper portion of the vessel is a seed crystal 48 mounted to the inside of the top of the cell, e.g, clamped or bonded to lid 55. Notably, in the configuration of FIG. 1, during processing the back surface of the seed 48 contacts the bottom surface of the lid 55, whether by physical attachment, such as adhesive or clamp, or by pressure differential, as explained in JP 2011-20860.
The entire vessel is surrounded with insulation 54 such as graphite felt or foam. The reaction cell 40 is placed in a vacuum furnace 70 which is pumped by a vacuum pump 90. The vacuum furnace 70 may be comprised of steel if the cell is resistively heated, or it may be comprised of dielectric, e.g., glass, if the cell is inductively heated. In the embodiments shown, the vacuum furnace is comprised of glass and is heated by an RF induction coil 72. Silicon and carbon evaporate from the source material 42 and condense onto the seed 48. Silicon and carbon that has not condensed onto the seed is diffused out of the reaction vessel and into the vacuum furnace. This diffusion is driven by pressure gradient between the interior of the reaction vessel and the vacuum furnace. Gases that are being injected into the vacuum furnace, such as nitrogen (82, 84), argon (86, 88), and dopants, diffuse through the graphite crucible walls and into the reaction vessel. This diffusion is driven by concentration gradient between the vacuum chamber and the interior of the reaction vessel.
When methods to produce larger crystals emerged, focus also moved to control defects in the crystals. Defects can be categorized as inclusions and crystal dislocations. The primary crystalline defects in SiC crystals are screw dislocations. Among these are a special case known as micropipes or hollow core screw dislocations. Additionally, there are basal plane dislocations and threading edge dislocations. These defects originate from many sources. For example, defects contained in the seed crystal can be passed to the newly grown crystal volume. Stresses arising from temperature gradients and thermal expansion mismatch and imparted to the seed and crystal during growth can result in formation of dislocations. Deviation of the stoichiometry in the sublimation vapor stream from that needed to form SiC can result in unstable polytype growth—in turn leading to polytype inclusions in the grown crystal, which lead to dislocation formation at the polytype boundaries. Even interactions between dislocations can create or eliminate dislocations.
SiC crystals produced by methods identified have large concentrations of dislocations. As of this filing, the commonly reported values of screw dislocation and basal plane concentration are nominally 5000-10000/cm2, respectively. The dislocations are most commonly assessed by sectioning the crystal in the plane normal to the crystal axis of symmetry. Etching the exposed crystal surface with molten salt, like potassium hydroxide, at temperatures in the 350-500 C range will reveal the dislocations. Each dislocation type has a unique shape so they can be uniquely counted. The dislocations are commonly counted and reported as a number divided by the inspection area. This characterization method is useful as it allows for easy correlation of defects contained in planar semiconductor devices formed on the crystal plane. There are many examples in the literature which show that dislocations are not uniformly distributed in the plane of observation. The large count of dislocations makes it very impractical to count every single one, especially as today inspections can be required on sections greater than or equal to the equivalent of 100 mm diameter circles. So the etched area is sampled to determine the amount of dislocations. Incorrect sampling methods can lead to errors in the estimation of the dislocation concentration associated with larger crystals. In most reports, the details of the sampling method are not provided, so replication of results can often be difficult, if not impossible.
Scientists experienced in solid state physics and semiconductor devices know that dislocations result in device performance below the theoretical properties of the material. Therefore, modern effort focused on improvements of semiconductor SiC crystal quality look to identify and control the factors which can reduce defects originating in crystal growth.
Once large enough crystals are produced, the crystal must be cut and fabricated into wafers to fit into equipment for fabricating semiconductor devices using planar fabrication methods. As many semiconductor crystals (e.g. silicon, gallium arsenide) have been successfully developed and commercialized into wafer products, the methods to fabricate wafers from bulk crystals are known. A review of the common approaches to, and requirements for wafer fabrication and standard methods of characterization can be found in Wolf and Tauber, Silicon Processing for the VLSI Era, Vol 1—Process Technology, Chapter 1 (Lattice Press—1986).
Due to its hardness, fabrication of SiC into wafer substrates presents unique challenges compared to processing other common semiconductor crystals like silicon or gallium arsenide. Modifications must be made to the machines and the choices of abrasives changed beyond commonly used materials. The modifications made on common wafer fabrication techniques in order to accommodate SiC are often kept as proprietary information. It has been reported that substantial subsurface damage is observable on mirror polished SiC wafers, and this can be reduced or removed by using chemical enhanced mechanical polishing methods similar to that used in the silicon industry (Zhou, L., et al., Chemomechanical Polishing of Silicon Carbide, J. Electrochem. Soc., Vol. 144, no. 6, June 1997, pp. L161-L163).
In order to build semiconductor devices on SiC wafers, additional crystalline SiC films must be deposited on the wafers to create the device active regions with the required conductivity value and conductor type. This is typically done using chemical vapor deposition (CVD) methods. Techniques for growth of SiC by CVD epitaxy have been published from groups in Russia, Japan and the United States since the 1970's. The most common chemistry for growth of SiC by CVD is a mixture of a silicon containing source gas (e.g monosilanes or chlorosilanes) and a carbon containing source gas (e.g. a hydrocarbon gas). A key element to growth of low defect epitaxial layers is that the substrate surface is tilted away from the crystal axis of symmetry to allow the chemical atoms to attach to the surface in the stacking order established by the substrate crystal. When the tilt is not adequate the CVD process will produce three dimensional defects on the surface, and such defects will result non-operational semiconductor devices. Surface imperfections, such as cracks, subsurface damage, pits, particles, scratches or contamination will interrupt the replication of the wafer's crystal structure by the CVD process (see, for example, Powell and Larkin, Phys. Stat. Sol. (b) 202, 529 (1997)). It is important that the polishing and cleaning processes used to fabricate the wafer minimize surface imperfections. In the presence of these surface imperfections several defects can be generated in the epitaxial films including basal plane dislocations and cubic SiC inclusions (see for example, Powell, et. al. Transactions Third International High-Temperature Electronics Conference, Volume 1, pp. II-3-II-8, Sandia National Laboratories, Albuquerque, N. Mex. USA, 9-14 Jun. 1996).
Defects in SiC are known to limit or destroy operation of semiconductor devices formed over the defects. Neudeck and Powell reported that hollow core screw dislocations (micropipes) severely limited voltage blocking performance in SiC diodes (P. G. Neudeck and J. A. Powell, IEEE Electron Device Letters, vol. 15, no. 2, pp. 63-65, (1994)). Neudeck reviewed the impact of crystal (wafer) and epitaxy originated defects on power devices in 1994, highlighting limitations of power device functionality due to screw dislocations and morphological epitaxy defects (Neudeck, Mat. Sci. Forum, Vols 338-342, pp. 1161-1166 (2000)). Hull reported shift to lower values in the distribution of high voltage diode reverse bias leakage current when the diodes were fabricated on substrates having lower screw dislocation density (Hull, et. al., Mat. Sci. forum, Vol. 600-603, p. 931-934 (2009)). Lendenmann reported forward voltage degradation in bipolar diodes was linked to basal plane dislocations in the epilayer that originate from basal plane dislocations in the substrate (Lendenmann et. al., Mat. Sci. Forum, Vols 338-342, pp. 1161-1166 (2000)).
While much progress has been achieved to improve SiC crystals and use the material as substrates for transistors and diodes, adoption of the processes and devices in mainstream power electronics has been slow. Today, most power semiconductor device manufacturing is done with silicon substrates of diameter 150 mm or larger. These substrates have extreme requirements for purity, surface contamination, particles, thickness uniformity and flatness. Purity and surface contamination issues on silicon substrates are critical in a silicon device fabrication process as the common impurities will diffuse in silicon and then aggregate at surfaces leading to poor performance in devices fabricated on the substrate surfaces. Power device fabrication uses relatively large die size and to achieve high fabrication and operation yield the crystal quality of the substrate material reflects a high degree of perfection. Modern methods for fabrication of power devices use silicon substrates which have perfect crystal quality, i.e. low dislocation density and low surface defects.
Semiconductor SiC is a promising material for the next generation power semiconductor devices. Adoption of SiC wafers for power electronics manufacturing has been slow since most SiC substrates produced have relatively small diameter (76-100 mm), have large defect density and are more expensive than silicon. The use of wafers other than silicon with diameter less than 150 mm makes power device manufacturing more costly and adds complexity to handle the small wafers with equipment designed for diameters of 150 mm or larger. To solve the problem of adoption, a SiC substrate process must be developed which can emulate all the following attributes:                Wafer diameter of 150 mm or larger        Wafer thickness, bevel and flatness comparable to the analogous silicon wafer or compatible with silicon process equipment        Very low crystalline defect density        Very low levels of surface contamination so as to prevent cross contamination with silicon processes performed on shared equipment.        Compatibility with SiC epitaxy to enable substrate suitable for device manufacturing.        
Growth of SiC crystals with diameter equal to or larger than 150 mm is very difficult. Traditional sublimation methods are limited by the amount of Si/C source material that can be contained in the reaction cell. To grow a crystal of 150 mm diameter or larger requires extreme amounts of source material which can take up much volume in the reaction cell and furnace. This dictates a very large reaction cell. Larger cell geometry can result in large radial and axial temperature gradients, which in turn lead to large stresses in the crystal and or excessive growth rates. The stresses result in defect formation in the crystal while large growth rates lead to challenges in controlling the polytype of the crystal. Large defect density (total dislocations greater than 2E4/cm2) are not low enough to make reliable power devices. A compact cell design may limit temperature gradients, even to the point where there is not enough driving force to support vapor transport and the resulting crystals are very small, impractical for cutting substrates.
Discussion of crystals of SiC with diameter of 150 mm and low dislocation density is discussed in the prior art. Fujimoto, U.S. 2010/0295059 A1, discloses a method of growing SiC crystals with low dislocation density by sublimation with comments that the method can support the ability to grow crystals to diameter of 250 mm, but the examples provided are all below 100 mm diameter. Fujimoto argues the extension of the process to diameter of up to 250 mm purely on the basis of dislocation density control and without any insight as to how to scale the sublimation process to accommodate large crystals. Nakabayashi, US 201110206929 A1 discloses a method of growing SiC crystals with low dislocation density by sublimation with comments that the method can support the ability to grow crystals to diameter of 300 mm, but the examples are all in the range of 75-105 mm. Like Fujimoto, any detail on the scaling of the process to accommodate large crystals is absent; only the method of defect control is discussed. Other references disclosing large diameter wafers include U.S. Pat. No. 8,747,982 and U.S. Pat. No. 8,741,413.
Kondo (Mat. Sci. Forum Vols. 778-780 (2014) p. 17) discloses a method for growing crystals of silicon carbide of 150 mm diameter by a method known as the repeated A face method. The results show low defect density. Kondo does not discuss details pertaining to the extension of the method for producing 4H—SiC crystals with diameters larger than 150 mm by sublimation.
None of the aforementioned patents disclose methods of making large diameter substrates from the large crystals of SiC that are suitable for use in the fabrication of power devices. Moreover, none raises or addresses the issue of thermal gradient and stresses that can be developed when using larger r4eaction cells for larger crystals.